1. Field of the Invention
The present invention relates to testing of integrated circuits (ICs), and more particularly to reducing the number of probes necessary to test logic blocks of an integrated circuit before the integrated circuit is packaged.
2. Description of Related Art
Integrated circuits are mass produced on semiconductor wafers. Typically, the integrated circuits are formed to occupy a rectangular area of a semiconductor wafer. Before packaging, the integrated circuit on the rectangular semiconductor material is called a die. The semiconductor wafer, which is typically round, contains many dies. Depending on the size of the wafer and the size of the die a single wafer can contain hundreds of dies. FIG. 1 shows a simplified example of semiconductor wafer 100 containing thirty-seven dies 110.
The cost of packaging a die is a major factor in the overall production cost of a chip. Therefore, a die is often tested prior to packaging to prevent needless packaging of a non-functional die.
Furthermore, the dies are typically tested before the semiconductor wafer is cut into individual dies. Therefore, if the vast majority of the integrated circuits are non-functional, the cost of cutting the wafer can be avoided. In addition, handling of the semiconductor wafer during testing is easier than handling each individual die.
Typically during wafer testing, probes are placed on the bonding pads of a die. The probes either supply signals to input bonding pads or monitor signals on the output bonding pads. FIG. 2 shows a simplified representation of a single die containing a microprocessor. In FIG. 2, die 200 contains forty bonding pads 205 which would correspond to forty pins of a packaged chip. A real microprocessor could contain over three hundred bonding pads.
Except for power bonding pads 207 and ground bonding pads 208, bonding pads 205 are coupled to corresponding interface cells 210. Each interface cell 210 could be a dedicated input cell, a dedicated output cell, or an input/output (I/O) cell. As used herein, input cell refers to both dedicated input cells and input/output cells. Die 200 also contains various logic blocks. For a microprocessor, the logic blocks can include data cache 210, instruction cache 220, memory management unit (MMU) 230, floating point unit (FPU) 240, integer unit 250, branch prediction unit 260, mode select unit 270, for example.
While testing a die, all of the bonding pads coupled to input cells (i.e. dedicated input cells or input/output cells) must be connected to a probe to provide a definite logic level on the pads. The term input bonding pad as used herein refers to a bonding pad that is coupled to an input cell. If an input bonding pad is not connected to a probe the pad "floats" at an indefinite logic level. The interface cells coupled to the floating pad provide an indeterminate floating signal to the various logic cells. Floating signals on the die cause spurious signals which makes testing inaccurate.
Even if only a single logic block is being tested, all of the input bonding pads must be forced to a definite logic level. For example, if a test is to be performed only on data cache 210, even bonding pads which are coupled to input cells which are not coupled to data cache 210 must be driven by a probe to a definite level. For example, bonding pad 281, which is coupled to input cell 212, must still be coupled to a probe so that bonding pad 281 is driven to a definite level; eventhough, input cell 212 is only coupled to FPU 240. Similarly, if only FPU 240 is being tested, bonding pad 281, which is coupled to input cell 211, must be driven to a definite level; eventhough, input cell 211 is only coupled to integer unit 250.
As integrated circuits have transitioned to smaller geometry sizes, the complexity of integrated circuit has increased. The increasing complexity leads to higher integration which requires increasing number of bonding pads for communications into and out of a chip. However, for many complex chips, such as microprocessors, the number of bonding pads has made connecting a probe to each bonding pad very difficult and time consuming.
Some chips have incorporated passive devices such as pull-up resistors between the input lines and the positive supply voltage to provide definite logic levels. However, this method degrades the performance of the chip in normal (i.e. non-test) modes since the drive supplied by the pull-up resistor must be overcome by the input signal or the output signal on an input/output line. Furthermore, this method is not feasible in complex high density circuits since passive devices such as resistors consume too much area.
Hence, there is a need for a method or a circuit to provide definite logic levels on bonding pads of a die during testing without the need of driving every bonding pad from an external source and without degrading the normal performance of the die. Specifically, the method or circuit must be able to drive input cells (i.e. dedicated input cells and input/output cells) to definite logic levels without a probe being connected to the input bonding pads. Furthermore, the circuit and method must not hamper the operation of the integrated circuit in non-test circumstances.